CY7C107D cy7c1007d 1-mbit (1m x 1) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05469 rev. *e revised february 22, 2007 features ? pin- and function-compatible with cy7c107b/cy7c1007b ? high speed ?t aa = 10 ns ? low active power ?i cc = 80 ma @ 10 ns ? low cmos standby power ?i sb2 = 3 ma ? 2.0v data retention ? automatic power-down when deselected ? cmos for optimum speed/power ? ttl-compatible inputs and outputs ? CY7C107D available in pb-free 28-pin 400-mil wide molded soj package. cy7c1007d available in pb-free 28-pin 300-mil wide molded soj package functional description [1] the CY7C107D and cy7c1007d are high-performance cmos static rams organized as 1,048,576 words by 1 bit. easy memory expansion is provided by an active low chip enable (ce ) and tri-state drivers. these devices have an automatic power-down feat ure that reduces power consumption by more than 65% when deselected. the output pin (d out ) is placed in a high-impedance state when: ? deselected (ce high) ? when the write operation is active (ce and we low) write to the device by taking chip enable (ce ) and write enable (we ) inputs low. data on the input pin (d in ) is written into the memory location spec ified on the address pins (a 0 through a 19 ). read from the device by taking chip enable (ce ) low while while forcing write enable (we ) high. under these condi- tions, the contents of the memory location specified by the address pins appears on the data output (d out ) pin. logic block diagram sense amps power down ce we a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 row decoder 1m x 1 array input buffer a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 column decoder d in d out a 19 a 18 note 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress application note, available on t he internet at www.cypress.com . [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 2 of 10 pin configuration [2] selection guide CY7C107D-10 cy7c1007d-10 unit maximum access time 10 ns maximum operating current 80 ma maximum cmos standby current, i sb2 3ma 1 2 3 4 5 6 7 8 9 11 14 15 16 20 19 18 17 21 24 23 22 12 13 25 28 27 26 a 16 a 10 a 11 a 12 a 13 a 14 a 7 nc a 17 a 18 a 19 nc a 4 a 6 a 3 we a 15 ce d in a 0 a 1 a 2 v cc gnd 10 top view soj d out a 5 a 8 a 9 note 2. nc pins are not connected on the die. [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 3 of 10 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..................................... ? 65c to +150c ambient temperature with power applied .................................................. ? 55c to +125c supply voltage on v cc relative to gnd [3] ....? 0.5v to +6.0v dc voltage applied to outputs in high-z state [3] ...................................... ? 0.5v to v cc + 0.5v dc input voltage [3] .................................. ? 0.5v to v cc + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40c to +85c 5v 0.5v 10 ns electrical characteristics (over the operating range) parameter description test conditions 7c107d-10 7c1007d-10 unit min max v oh output high voltage i oh = ? 4.0 ma 2.4 v v ol output low voltage i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage [3] ? 0.5 0.8 v i ix input leakage current gnd < v i < v cc ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz 80 ma 83 mhz 72 ma 66 mhz 58 ma 40 mhz 37 ma i sb1 automatic ce power-down current? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max 10 ma i sb2 automatic ce power-down current? cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 3ma note 3. v il (min) = ?2.0v and v ih (max) = v cc + 1v for pulse durations of less than 5 ns. [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 4 of 10 capacitance [4] parameter description tes t conditions max unit c in : addresses input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 7 pf c in : controls 10 pf c out output capacitance 10 pf thermal resistance [4] parameter description test conditions 300-mil wide soj 400-mil wide soj unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 59.16 58.76 c/w jc thermal resistance (junction to case) 40.84 40.54 c/w ac test loads and waveforms [5] 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 3 ns fall time: 3 ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 5v output 5 pf (c) r1 480 ? r2 255 ? high-z characteristics: including jig and scope notes 4. tested initially and after any design or proce ss changes that may affect these parameters. 5. ac characteristics (except high-z) are te sted using the load conditions shown in fi gure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 5 of 10 switching characteristics (over the operating range) [6] parameter description 7c107d-10 7c1007d-10 unit min max read cycle t power [7] v cc (typical) to the first access 100 s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce low to data valid 10 ns t lzce ce low to low z [8] 3ns t hzce ce high to high z [8, 9] 5ns t pu [10] ce low to power-up 0 ns t pd [10] ce high to power-down 10 ns write cycle [11] t wc write cycle time 10 ns t sce ce low to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 6 ns t hd data hold from write end 0 ns t lzwe we high to low z [8] 3ns t hzwe we low to high z [8, 9] 6ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 8. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe for any given device. 9. t hzce and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ?ac test loads and waveforms [5]? on page 4 . transition is measured when the outputs enter a high impedance state. 10. this parameter is guaranteed by design and is not tested. 11. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 6 of 10 data retention characteristics (over the operating range) parameter description conditions min max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 3ma t cdr [5] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 (address transition controlled) [13, 14] read cycle no. 2 [14, 15] 4.5v 4.5v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzce t pu high impedance t hzce t pd high i cc i sb impedance address ce data out v cc supply current notes 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 s or stable at v cc(min) > 50 s. 13. device is continuously selected, ce = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 7 of 10 write cycle no. 1 (ce controlled) [16] write cycle no. 2 (we controlled) [16] truth table ce we d out mode power h x high z power-down standby (i sb ) l h data out read active (i cc ) l l high z write active (i cc ) switching waveforms (continued) data valid t sce t aw t sa t pwe t ha t hd t sd t wc high impedance address ce we data out data in t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd address ce we data out data in note 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C107D-10vxi 51-85032 28-pin (400-mil) molded soj (pb-free) industrial cy7c1007d-10vxi 51-85031 28-pin (300-mil) molded soj (pb-free) please contact your local cypress sales representative for availability of these parts. package diagrams figure 1. 28-pin (400-mil) molded soj, 51-85032 pin 1 i.d .435 .395 .445 .405 .128 .148 .360 .380 .026 .015 .032 .020 dimensions in inches min. max. .025 min. .007 .013 .050 typ. .720 .730 1 14 15 28 0.004 seating plane 51-85032-*b [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 9 of 10 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 2. 28-pin (300-mil) molded soj, 51-85031 all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c [+] feedback [+] feedback
CY7C107D cy7c1007d document #: 38-05469 rev. *e page 10 of 10 document history page document title: CY7C107D/cy7c1007d, 1-mbit (1m x 1) static ram document number: 38-05469 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233722 see ecn rkf dc parameters modified as per eros (spec # 01-02165) pb-free offering in ordering information *b 263769 see ecn rkf added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307601 see ecn rkf reduced speed bins to ?10 and ?12 ns *d 560995 see ecn vkn converted from preliminary to final removed commercial operating range removed 12 ns speed bin added i cc values for the frequencies 83mhz, 66mhz and 40mhz updated thermal resistance table updated ordering information table changed overshoot spec from v cc +2v to v cc +1v in footnote #3 *e 802877 see ecn vkn changed i cc specs from 60 ma to 80 ma fo r 100mhz, 55 ma to 72 ma for 83mhz, 45 ma to 58 ma for 66mhz, 30 ma to 37 ma for 40mhz [+] feedback [+] feedback
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